1. Field of the Invention
The present invention relates to a decoupling capacitor and a semiconductor integrated circuit using the same.
2. Description of Related Art
In recent years, along with improvement in speed and advanced features of a digital circuit, an improvement in speed and a high-density integration of a semiconductor integrated circuit have been made progress. Power consumption of a chip has increased due to the improvement in speed and the high-density integration of the semiconductor integrated circuit and a supply voltage drop (IR-DROP) has posed a problem in connection with it, and there have arisen problems that switching speed of a transistor has been decreased due to a supply voltage drop, resulting in a decrease in operating frequency of a circuit, and noise margin has been decreased due to the supply voltage drop and mislatch of data or the like has been generated, resulting in a circuit malfunction. For that reason, in order to increase a speed of the semiconductor integrated circuit and improve stability of a circuit operation, in a high-speed semiconductor integrated circuit, there is taken a countermeasure that a decoupling capacitor with capacitance of not less than nanofarads is inserted between a power supply and a ground within the circuit and a current is supplied from the decoupling capacitor against an internal rapid peak current, thereby making it hard to generate a supply voltage drop.
As a method of forming the decoupling capacitor in the semiconductor integrated circuit, there are a method of using a gate oxide film of a transistor and a method of using an overlap capacitance of interconnections or the like. In the method of using a overlap capacitance of interconnections, the capacitance is formed with interconnections arranged in parallel and a response speed of the capacitance is high because of a small resistance, whereas in order to prevent a short circuit between the interconnections, it is necessary to increase a space between the interconnections (interconnection space), but since the interconnection space cannot be reduced, a capacitance value per unit area is small, thereby making it difficult to form a capacitor with a large capacitance. In the meantime, in the method of using a gate oxide film of a transistor, since the gate oxide film thickness is very thin, the capacitance value per unit area becomes large, so that it is possible to form a capacitor having a capacitance of nanofarads but there is a problem that a leakage current increases or reliability decreases due to transistor breakdown caused by ESD or the like. In FIG. 14, there is shown an example of a structure of a decoupling capacitor using a gate oxide film of a P-channel transistor. In FIG. 14, a gate portion 103 of the transistor is connected to VSS 102, and a source portion 104, a drain portion 105, and a substrate portion 106 are connected to VDD 101. Therefore, a capacitance is formed between a gate and a channel through the gate oxide film.
Moreover, with a microfabrication of the semiconductor integrated circuit, although a gate oxide film thickness of a transistor has become thin and a gate length of the transistor has become short, a supply voltage has not been reduced so as to be proportional to it, so that a leakage current has increased. There are three kinds of current which flow through a transistor, such as switching current, through current, and leakage current (FIG. 15). In FIG. 15, a switching current 201 is a current which is consumed for the transistor to drive an interconnection or to pull up and down a gate capacitance of the next stage, and a through current 202 is a current which flows from a P-channel transistor to an N-channel transistor, since both the P-channel transistor and the N-channel transistor are temporarily opened when an output signal changes. In addition, a leakage current 203 is a current which flows from a source to a drain, and from a gate to the drain and a substrate, and a current which always flows even when a circuit is not in operation.
The leakage current does not cause a problem so much in normal operation because of its very small value compared with the switching current or the through current. But when the circuit is not in operation, such as in a standby mode, a lower power dissipation is particularly required. Because neither the switching current nor the through current flows, but the leakage current flows, a reduction in the leakage current in the standby mode is required. When the decoupling capacitor of not less than nanofarads using the gate oxide film is arranged in a chip, the leakage current due to only the decoupling capacitor will possibly be milliamperes, and the more the decoupling capacitors are inserted therein for a countermeasure against a supply voltage drop, the more the leakage current increases, so a reduction in the leakage current of the decoupling capacitor is required. As a method of reducing the leakage current of the decoupling capacitor, there is a method of thickening the gate oxide film, and in that case, a reduction in capacitance per unit area due to the gate oxide film thickness being thicker, and a reduction in capacitance due to a decrease in a gate area of the decoupling capacitor since it is necessity to increase a space to a transistor of a logic cell due to a process factor or the like are caused, thereby making it difficult to ensure sufficient capacitance.
A cell structure of the decoupling capacitor constituted so that a leakage current may not flow in a standby mode is disclosed in Patent Literature 1. According to this technology, by controlling a potential provided to one electrode of the above decoupling capacitor using an inverter, in normal operation, the above decoupling capacitor is used as a capacitor by setting both electrodes thereof at different potentials, and in a standby mode, both electrodes of the decoupling capacitor are set at the same potential so that a capacitance is not generated, thereby making a leakage current not to flow.
A structure of the semiconductor integrated circuit for controlling a leakage current by controlling a substrate is also disclosed in Patent Literature 2. According to this technology, by applying a reverse bias voltage to a substrate in a standby mode, a threshold value of the transistor is increased, so that a drive current of the transistor is decreased, thereby reducing a leakage current.
It is recommended to refer to Japanese Laid-Open Patent Application Publication No. 7-245378 as Patent Literature 1, and the Japanese Patent Publication No. 3105512 as Patent Literature 2.
However, according to the conventional structures of the above decoupling capacitor, it will become such a structure that a resistance between the source and the drain of the transistor for controlling the potential of the electrode is inserted between a power supply of the decoupling capacitor and a ground, resulting in a structure where a capacitor and a resistance are connected in series. Since the resistance between the source and the drain of the transistor has been large, when using it as the decoupling capacitor in normal operation, there has been a problem that a response of the capacitance has become worse.
Moreover, according to the method of reducing the leakage current by controlling the substrate like prior art, a circuit operation has also become worse in attempting to reduce the leakage current of the decoupling capacitor, so that it has not been able to gradually change a leak current value and a capacitance value according to working speed.